Ten Lessons from My First Custom PCB

Rev A of my macropad PCB didn’t enumerate. Rev B enumerated but browned out when all twelve LEDs lit. Rev C works. Three spins, about $14 in boards and $30 in shipping from JLCPCB, and a pile of lessons that every guide mentions and I ignored anyway. Here are the ten that cost me the most.

1–3: Footprints will hurt you first

Verify every footprint against the datasheet, not the library name. My USB-C receptacle footprint (a generic “USB_C_Receptacle_16P” from a community library) had shield tabs 0.3 mm off from the HRO TYPE-C-31-M-12 I actually ordered. The connector sat crooked and two pads never wetted. Rev A, dead on arrival.

Print the layout 1:1 on paper and place real parts on it before ordering. Thirty seconds with a glue stick would have caught the connector problem.

Pin 1 orientation is not a convention, it’s a decision. I rotated the RP2040’s QFN-56 footprint 90° while “tidying” the layout and didn’t re-check the dot. The DRC can’t save you from a part that’s electrically valid and physically wrong.

4–5: Power integrity is not optional

The RP2040 datasheet asks for a 100 nF cap per supply pin plus bulk capacitance, placed close. I gave it three caps total, sprinkled wherever they fit. Rev B reset itself whenever the SK6812 LEDs drew a current step. Rev C has a 100 nF within 2 mm of each of the nine supply pins and a 10 µF bulk cap per rail:

Rule I now follow: place decoupling caps BEFORE routing anything.
Caps first, then crystal, then USB, then everything else.

Also: my LED rail needed 12 × 60 mA worst case. I’d routed it with a 0.25 mm trace. At 720 mA that’s a heater, not a trace. 1 mm minimum on power now.

6: USB differential pairs, the boring version

Full-speed USB (12 Mbps) is forgiving, but I still did it properly in KiCad: routed D+/D− as a pair with Route > Differential Pair, kept them length-matched within 0.5 mm, no vias, ground pour underneath, and the 27 Ω series resistors within 5 mm of the RP2040. Impedance control at these speeds is mostly theater on a 1.6 mm 2-layer board, but the discipline costs nothing.

7: Silkscreen is free debugging

Rev C’s silkscreen has: net names next to every test point, LED index numbers, a “USB →” arrow, and the revision string. When something misbehaves I probe TP_3V3 instead of counting pins under a microscope. Silkscreen costs nothing at JLCPCB. Use all of it.

8: DRC is a gate, not a suggestion

I now run DRC with zero suppressed warnings before every export, plus a custom rule for the JLCPCB 6-mil minimum:

(rule "jlc_min_clearance"
  (constraint clearance (min 0.152mm))
  (condition "A.Type == 'track'"))

Rev A shipped with two “courtyard overlap” warnings I’d dismissed. One of them was the crooked USB connector telling me about itself.

9: 0402 was a mistake

I chose 0402 passives because the board is small and it felt professional. Hand-reflowing them with a hot plate and a stencil is fine; reworking them is misery. Every decoupling cap I had to move during Rev B debugging took ten minutes and tweezers I don’t own good enough versions of. 0603 everywhere on Rev C. The board got 4% bigger. Nobody noticed.

10: Panelize, or don’t

I mouse-bit two boards into one panel to halve the per-board cost. The tabs left rough edges that needed filing, and JLCPCB charges a panelization fee that ate most of the savings at qty 5. Below ~20 boards, just order singles.

Rev	Fault	Fix
A	Wrong USB-C footprint, ignored DRC	Verified footprint, DRC gate
B	Under-decoupled, thin power traces	Cap-per-pin, 1 mm rails
C	Works	—

Two respins felt like failure at the time. In hindsight they were the tuition.